The present invention relates to very large scale integrated circuits, and to methods for fabrication thereof.
Interconnect technology is increasingly a major limitation in the fabrication of very large scale integrated circuits. In particular, the use of multiple patterned polysilicon or metal layers for interconnects places great pressure on the processing technology related to etching of contact holes and planarization of interlevel dielectrics. However, the additional routing capability which is provided by any additional level of interconnect will often give circuit designers options which translate into more compact layouts, better circuit performance, and/or greater ease of circuit design.
For these reasons much effort has been dedicated to modifying processes to include a buried contact. A buried contact process is a process which uses a single layer to form not only MOS gates, but also, using other patterned portions of the same layer, contact to the source/drain regions of MOS transistors. That is, the same thin film polysilicon or polycide layer must in some locations be separated from the moat by a very thin high-integrity gate oxide, and in other locations must form an ohmic contact to highly doped moat regions. This leads to three main classes of processing problems: first, gate oxide integrity becomes more difficult to preserve. Second, scalability is limited by interdiffusion between the polysilicon material and the bulk silicon. That is, phosphorus doping used to make the polysilicon conductive will normally outdiffuse into the silicon substrate at the contact location. However, as devices are scaled to small geometries, this phosphorus diffusion can counterdope a major fraction of the channel stop doping, leading to leakage between active areas. Third, first contacts are highly desirable in CMOS processing, but present technology does not provide any manufacturable process to make contact to P+ moat regions. Not only is there the problem of how to avoid a diode between N+ poly and P+ substrate, but similar problems of dopant outdiffusion may lead to shorting from the poly to the PMOS substrate at first contacts to P+.
There have been published suggestions of ways to provide a local interconnect level in the context of a self-aligned titanium silicide process for source/drain silicidation. The self-aligned titanium silicide source/drain silicidation process is disclosed in U.S. patent application Ser. No. 492,069, filed May 6, 1983, U.S. Pat. No. 4,454,116, which is hereby incorporated by reference. In this process, metallic titanium is deposited overall, and is then heated in a nitrogen atmosphere so that the titanium reacts with exposed silicon surfaces (such as source/drain regions, or exposed upper surfaces of polysilicon lines) to form titanium silicide. The portions of titanium which did not react to form silicides are then stripped (using, for example, a wet etch). This process provides a self-aligned silicidation process without any patterning steps. This self-aligned silicidation process has come into wide use in integrated circuit fabrication.
The previously proposed local interconnect schemes based on this process use additional patterned silicon to provide conductive silicide regions extending out over the field oxide as desired. That is, in the process developed by Hewlett Packard and published at Page 118 of the 1984 IEDM Proceedings, (which publication is hereby incorporated by reference), after the titanium metal is deposited overall, and before heat is applied to effect silicide reaction, a thin layer of silicon (either polycrystalline or amorphous) is patterned on top of the titanium metal. Where this silicon layer has been applied, a silicide will form during the reaction process, so that silicides can be formed extending over the gate sidewall oxide or over the field oxide. A similar approach previously developed at Texas Instruments used patterned silicon straps which were applied before the titanium metal was applied.
However, both of these approaches have the limitation that deposition of an additional layer is required. Thus, both of these approaches contain excess processing complexities.
Other publications relevant to examination of the present application may be found in the paper by C. Y. Ting at page 110 of the 1984 IEDM proceedings (and see especially page 113) and in the paper by M. Alperin et al., Development of the Self-aligned TiSi.sub.2 Process for VLSI applications, at page 141 of the February 1985 issue of the IEEE transactions on Electron Devices.
The present invention provides a simpler method of forming local interconnects in the context of a self-aligned direct-react titanium silicide process for source/drain (and preferably gate) silicidation.
It has been discovered that when the direct-react titanium silicide silicidation process is performed in a nitrogen atmosphere, a layer of titanium nitride (TiN) is formed in the titanium metal layer over field oxide. Thus, after the silicide reaction occurs, the portions of the deposited titanium metal layer which have not been in contact with a source of silicon (and therefore have not formed silicide) are not merely unreacted titanium metal, as was previously thought, but include a large fraction of titanium nitride. The present invention makes use of this newly discovered titanium nitride layer to provide a new and advantageous local interconnect method and structure.
After the silicidation step, the titanium nitride layer is patterned and selectively removed from titanium silicide and silicon oxide regions where it is not desired. After this, a final anneal is performed at higher temperature (e.g. 800.degree. C.) to reduce the final sheet resistance of the titanium silicide layers to below one ohm per square.
It is well-known in the integrated circuit art that titanium nitride is conductive, and the use of titanium nitride as a conductive diffusion barrier in contacts has been previously published; but not work published prior to the filing date of the parent application is known to discuss the use of titanium nitride to provide local interconnects, as in the present invention.
In a 1985 IEDM paper, researchers from Hewlett-Packard proposed applying a sputtered silicon layer over the deposited titanium metal, in a direct-react titanium silicidation process, before the reaction step, to provide patterned local interconnects of titanium silicide. These local interconnects were apparently thought at the time to provide advantages comparable to that of the titanium nitride interconnect of the present invention. However, not only does this approach require greater processing complexity, but it also fails to provide a crucial advantages of the present invention: the titanium silicide provides an efficient diffusion path for boron and phosphorous, and therefore problems of interdiffusion and counterdoping remain acute. By contrast, in the present invention the titanium nitride is a very good diffusion barrier, and these problems do not arise. The phosphorus counterdoping problems of the process shown in the HP 1985 paper may be confirmed by a more recent HP paper which describes a 16K static random access memory implemented with their TiSi.sub.2 strap process, but that only uses it to connect P-type and N-type junctions together. That is, the HP researchers did not use local interconnect to connect gates to junctions. In a design experiment to test the advantages of the present invention, researchers at Texas Instruments laid out a static random access memory cell according to the exact HP layout, i.e. where local interconnect is used to interconnect junctions, and where metal straps plus 2nd contacts are used to cross-couple the gates. In this HP process, the inability to interconnect both the gates and junctions with local interconnect results in a cell size, using 1 micron design rules, that is 75% larger than a cell with the same design rule geometries using TiN for local interconnect. This illustrates the advantage that TiN has over TiSi.sub.2 for performing the local interconnect function.
The ability to plasma etch TiN selectively with respect to TiSi.sub.2 permits easy fabrication of a structure wherein moat-to-moat interconnections have been formed using a very thin (e.g. 1000 Angstroms) layer of titanium nitride. This invention thus provides at least the following advantages:
1. Processing is simpler than in the methods for forming titanium silicide local interconnects discussed above. PA0 2. Since titanium nitride is a very good diffusion barrier, problems of interdiffusion through the silicide are avoided. This is particularly advantageous where the local interconnect layer is used to connect a p+ moat region to an n+ polysilicon gate or to an n+ moat region in CMOS processing. PA0 3. Titanium nitride local interconnects according to the present invention are most especially advantageous in providing local interconnect between an n+ polysilicon gate and a p-type moat region. Since the distances from gate to moat are typically much shorter than the n+ to p+ spacings, interdiffusion is a particularly acute problem here. PA0 4. Since the titanium nitride local interconnect layer can be made extremely thin, the amount of additional vertical topography induced in subsequent unplanarized layers is minimal. PA0 5. Since the titanium nitride layer is so thin, the etch used to remove it need not be anisotropic, which again simplies processing. PA0 6. Even a very thin titanium nitride layer can provide very low sheet resistances, of the order of five to ten ohms per square. PA0 7. The titanium nitride local interconnect layer can also be utilized to provide a diffusion barrier in place for contacts. That is, contacts to moat can deposit metal on top of the titanium nitride layer rather than directly on silicon, so that interdiffusion between metal and silicon is effectively prevented. This simplifies the selection of interconnect metalization. In particular, use of non-aluminum metallization now becomes much more practical. PA0 8. The overlap of the titanium nitride onto the field oxide means that the contact holes need not be perfectly aligned to the edge of the moat, but the contact hole can overlap onto the titanium nitride over the upper surface of the edge of the field oxide. PA0 9. The present invention provides a local interconnect layer of such good conductivity that strapping can be avoided in some applications, and thus the present invention will permit the elimination of double-level metal (DLM) process steps in some processes, without any sacrifice of speed or area. PA0 10. The number of second contacts in a layout can be reduced, since independent interconnection through a TiN layer can substitute for some metal interconnects. PA0 11. The present process is inherently amenable to shared contacts, i.e. to contacts where contact is made between two interconnect layers and substrate at the same location. This permits designers additional flexibility. PA0 12. The methods using silicon straps for local interconnect are inherently susceptible to open circuit defects where the silicon strap crosses the angle at the foot of the gate, and, to avoid this, the silicon straps need to be made relatively thick (as much as 2500 A thick in some processes), which degrades topography and throughput. By contrast, the TiN straps of the present invention do not have this problem, and therefore do not need to be made so thick. PA0 13. Titanium nitride is more resistant to oxide etches than titanium silicide is, so that damage caused by overetching the multilevel oxide at the contact etch step in a process using a planarized multilevel oxide are reduced. PA0 14. The capability of overlapping moat contacts up onto the field oxide means that minimum geometry can be used for the source/drain regions in the moat. PA0 15. The present invention permits connection between stages of CMOS logic to be accomplished without any contact holes, which provides advantages in area, speed, and yield. PA0 16. The present invention performs all the functions of a full buried contact capability, without the degradation in gate oxide integrity which commonly results from buried contact processes. PA0 17. The present invention performs all the functions of a full buried contact capability, without the degraded reproducibility of series resistance for ohmic contacts to p+ which commonly results from buried contact processes. PA0 18. The present invention performs all the circuit functions of a full buried contact capability, without the problem of shorting to an underlying n+ region where a local connection from polysilicon to a p+ source/drain region. PA0 1. providing a substrate; PA0 2. providing device isolation areas in a predetermined pattern to define moat regions in predetermined locations; PA0 3. fabricating insulated gate field effect transistors in predetermined locations in said moat regions; PA0 4. depositing a metal consisting substantially of titanium overall; PA0 5. heating said substrate and said titanium metal in a nitrogen-bearing atmosphere, so that said titanium metal reacts with exposed silicon portions of said substrate to form titanium silicides, and other portions of said titanium metal also react with said nitrogen atmosphere to form a layer having a large fraction of titanium nitride at the surface thereof; and PA0 6. patterning said titanium nitride layer to provide local interconnection in a predetermined pattern.
According to the present invention there is provided: A process for fabricating integrated circuits, comprising the steps of:
According to the present invention there is also provided: An integrated circuit device comprising:
a substrate; PA1 device isolation regions defining predetermined moat areas of exposed semiconducting material; PA1 a plurality of active devices near the surface of said moat areas; and PA1 a local interconnect layer, comprising lines consisting substantially of titanium nitride, interconnecting predetermined portions of said moat regions over said device isolation regions. PA1 a substrate; PA1 a plurality of NMOS transistors having PA1 a plurality of PMOS transistors having PA1 a plurality of local interconnects electrically linking selected ones of said gates of said NMOS transistors to selected ones of said gates of said PMOS transistors in predetermined locations, said local interconnects comprising a large fraction of titanium nitride. PA1 a plurality of static random access memory cells, each comprising PA1 first and second cross-coupled inverters, each said inverter comprising PA1 said gate of at least one of said pull-up and pull-down transistors of said first inverter being connected to a drain of at least one of said pull-up and pull-down transistors of said second inverter through a local interconnect layer, PA1 first and second cross-coupled inverters, each said inverter comprising PA1 first and second access transistors selectably connecting outputs of said first inverter to a first bit line and outputs of said transistors of said second inverter to a second bit line; PA1 wherein both of said respective pull-down transistors within each single one of said cells are formed in a common substrate and are separated one from another by field isolation regions. PA1 and wherein both of said respective pull-up transistors within each single one of said cells are formed in a common substrate and are separated one from another by field isolation regions, PA1 and wherein both of said respective access transistors connected to each single one of said cells PA1 1. providing a partially fabricated integrated circuit structure including moat regions, said moat regions incorporating active devices therein; PA1 2. depositing a thin layer of metal consisting predominantly of titanium overall; PA1 3. depositing a relatively inert material over said titanium in locations defining local interconnect pathways and/or locations of contacts to moat; PA1 4. reacting said partially fabricated structure in an atmosphere containing a high portion of nitrogen, whereby portions of said titanium metal over moat regions are predominantly converted to titanium silicide, and portions of said titanium metal over oxide regions are converted predominantly to titanium nitride; PA1 5. etching away exposed portions of said titanium and of said titanium nitride, to define local interconnects in predetermined local interconnect locations. PA1 1. providing a partially fabricated integrated circuit structure; PA1 2. providing a thin film which consists substantially of titanium nitride and which extends over a significant area of said partially fabricated integrated circuit structure; PA1 3. providing a patterned masking material over said titanium nitride thin film; and PA1 4. etching said titanium nitride thin film in a glow discharge formed from an input gas flow comprising a fluorine-liberating gas. PA1 1. providing a substrate; PA1 2. providing device isolation areas in a predetermined pattern to define moat regions in predetermined locations; PA1 3. forming a first patterned thin film conductor layer in predetermined locations; PA1 4. fabricating insulated gate field effect transistors in predetermined locations in said moat regions, said transistors comprising gates formed in a second patterned thin film conductor layer which comprises a large fraction of silicon; PA1 5. depositing a metal consisting substantially of titanium overall; PA1 6. heating said substrate and said titanium metal in a nitrogen-bearing atmosphere, so that said titanium metal reacts with exposed silicon portions of said substrate to form titanium silicides, and other portions of said titanium metal also react with said nitrogen atmosphere to form a layer having a large fraction of titanium nitride at the surface thereof; and PA1 7. patterning said titanium nitride layer to provide local interconnection among said substrate, said gates of said transistors, and said first conductor level in a predetermined pattern. PA1 a substrate; PA1 device isolation regions defining predetermined moat areas of exposed semiconducting material; PA1 first and second thin film conductor layers; PA1 a plurality of active devices near the surface of said moat areas; and PA1 a local interconnect layer, comprising lines consisting substantially of titanium nitride, interconnecting predetermined portions of said moat regions with predetermined portions of said first and second thin film conductor layers.
According to the present invention there is also provided: An integrated circuit device comprising:
substantially crystalline channel regions consisting essentially of silicon and located near the surface of said substrate, and PA2 gates which are substantially polycrystalline and comprise a large fraction of silicon and are doped n-type; PA2 substantially crystalline channel regions consisting essentially of silicon and located near the surface of said substrate, and PA2 gates which are substantially polycrystalline and comprise a large fraction of silicon and are doped p-type; and PA2 first and second cross-coupled inverters, PA2 each said inverter comprising PA2 and a pull-down transistor, PA2 all of said respective pull-down transistors within each individual one of said cells being separated one from another by a field oxide region. PA2 a pull-up transistor PA2 and a pull-down transistor, PA2 each said pull-up transistor and pull-down transistor PA2 said local interconnect layer having a minimum thickness less than that of said gate of said pull-up transistor of said first inverter PA2 and making ohmic contact directly to said gate and to said drain. PA2 a pull-up transistor PA2 and a pull-down transistor; and PA2 are formed in a common substrate PA2 and are separated PA2 by field isolation regions.
According to the present invention there is also provided: A static random access memory cell array, comprising
a pull-up transistor PA3 having a crystalline channel with a source connected to a substantially constant voltage PA3 and having an insulated gate capacitatively coupled to said channel PA3 and having a drain, PA3 one from another PA3 and from both of said pull-up transistors within said single cell PA3 and from both of said pull-down transistors within said single cell
A static random access memory cell comprising:
A static random access memory cell comprising:
According to the present invention there is also provided: A process for fabricating integrated circuits including local interconnect, comprising the steps of:
According to the present invention there is also provided: A process for fabricating integrated circuits, comprising the steps of:
According to the present invention there is also provided: A process for fabricating integrated circuits, comprising the steps of:
According to the present invention there is also provided: An integrated circuit device comprising: